1. Field of the Invention
The present invention relates to a reliability test equipment and a failure rate test equipment. More particularly, the present invention relates to a dynamic burn-in test equipment for testing large scale integration chips (LSI chips) sealed in packages each having a large number of I/O pins. Here, the LSI chips may include very large scale integration chips (VLSI chips), ultra large scale integration chips (ULSI chips) or gigascale integration chips (GSI chips).
2. Description of the Related Art
In recent years, the operation speeds, the memory capacities, and the numbers of bits of semiconductor devices are considerably increasing. As high-speed semiconductor devices, devices having operation frequency higher than 500 MHz, e.g., reduced instruction set computer (RISC) like microprocessor units (MPUs) have been developed. The number of pins of a package is also rapidly increasing. In this manner, the development of the semiconductor devices advances, new functions are successively added to the semiconductor devices. Accordingly, a testing technique such as a reliability test must keep in step with the development of devices. However, the development speed of semiconductor devices acceleratively increases, miscellaneous new functions to be added to the semiconductor devices become varied. Nowadays, the development speed of the testing technique is gradually behind the development speed of the semiconductor device. In particular, it has been very difficult to perform a reliability test for multi-pin LSI chips within a short test time and at a low cost.
In order to calculate failure rates of LSI chips as correct as possible, a large number of products must be tested for a very long test period. If the values of failure rates calculated as results of the test are equal to each other, the statistical "validities" of the failure rates are considerably different from each other depending on the numbers of tested products.
In general, the failure rate versus age (or "time in use") curve follows the well-known shape of the of the "bathtub curve" shown in FIG. 1. The failures are typically grouped into one of three categories: infant mortality, useful life, and wearout failures. The infant mortality failures, also called "early failures" or "patent failures" occur during early product life cycle, and by definition, the failure rate decreases with age. After the infant mortality failures are culled out, the component settle into a long period of useful life failure, called "over stress failures" or "intrinsic failures" which are caused by high-level stress outside those expected in normal usage. Finally, wearout failures begin to be significant as normal wear out mechanisms start to take their toll on components that are manufactured within acceptable specifications. Since the wearout failures occur considerably later than rated lifetime of semiconductor devices in general, the failure rate versus age curves in the infant mortality and the useful life stages are important. Therefore, in order to obtain meaningful qualification test data, the bathtub curve shown in FIG. 1 must be plotted so as to identify one of three failure mechanisms, by focusing on the failure rate versus age curve, calculated by the result of the test.
In general, "burn-in testing", or component testing where infant mortality failures are screened out by testing at elevated voltages and temperatures for a specified length of time, serving as an accelerated environment testing, is performed to plot in a short test period the failure rate versus age curves as shown in FIG. 1. On the assumption that the chemical reaction rate associated with the failure mechanism is expressed by an exponential function and has a positive temperature coefficient according to Arrhenius' equation, the test temperature is elevated to make the device failure conspicuous. Acceleration coefficient B of a failure rate is generally given by: EQU B=exp{-(.DELTA.E/k).multidot.(1/T.sub.jH 1/T.sub.jF)} (1)
where .DELTA.E: activation energy of a failure [eV], k: Bolzmann's constant=8.617.times.10.sup.-5 [eV/K], T.sub.jH : p-n junction temperature [K] of an LSI chip at the elevated temperature in the accelerated environment testing, and T.sub.jF : p-n junction temperature [K] of the LSI chip under normal and actual usage condition.
A perfect product must have an endless lifetime. More specifically, a limited lifetime is caused by the presence of any defect. If the defect is accelerated and increased by the elevated temperature under the test condition, the product is recognized as a defective. We can understand that the burn-in testing is conducted on the assumption that the long lifetimes of products that are able to pass the accelerated environment testing can be secured.
Since it is desirable to complete a reliability evaluation testing in a short test time, the reliability evaluation testing should be performed at an elevated temperature which is as high as possible. However, an annealing temperature is limited to a predetermined value because good products must not be damaged. According to such a consideration, the burn-in testing is performed at a limited elevated temperature at which the validity of acceleration can be recognized.
The characteristic feature of the burn-in testing is that the semiconductor device is tested at the elevated temperature, while supplying predetermined supply voltages. As a typical failure mechanism of LSI chips, an imperfect metallization or connection is known. Since the resistance of the interconnection is desired to be low, unexpected heat is generated at the interconnection where the resistance of the interconnection is high due to, for example, flaw, void, electromigration, corrosion, or non-ohmic contact. This means that a large acceleration coefficient is applied to only the weak portion.
When signals are given to an LSI, or a device under test (DUT) at random, all the internal circuits of the DUT cannot be operated. Therefore, a predetermined test pattern adjusted for an LSI test equipment is used for a reliability evaluation testing of the LSI chip. More specifically, in the burn-in testing, a test pattern generator (signal generator) having the same function as that of the LSI test equipment is required. Since the internal circuits of the LSI chip are operated by miscellaneous signals generated by the signal generator, such a test method for the LSI chip is called "dynamic burn-in testing". On the other hand, a burn-in testing in which any signal in the internal circuits of the LSI chip does not change at all under a high-temperature accelerated environment, while power supply lines are only connected to the LSI chip, is called "static burn-in testing". And, in this connection, a high-temperature accelerated environment testing in which even the power supply lines are not connected to the LSI chip is called a "high-temperature shelf life testing". Of the three test methodologies, the static burn-in testing and the high-temperature shelf life testing are mainly used at present. The static burn-in testing generally requires 8 to 16 hours. However, since the dynamic burn-in testing can drive all the internal circuits in the LSI chip, a local temperature in the LSI chip increases, and the dynamic burn-in testing is expected to be able to perform a testing in a shorter test period than that of the static burn-in testing. However, in a conventional static burn-in technique, the static burn-in testing requires very long test time. That is, the conventional static burn-in technique can be performed only when the numbers of pins of LSI chip serving as DUT are very small, and the number of DUTs must be small. In addition, the burn-in test equipment is expensive, and a running cost is high. For this reason, the dynamic burn-in testing is actually used in only a very limited situation.
FIG. 2 shows the outline of the conventional general dynamic burn-in test equipment used in the burn-in testing described above. As shown in FIG. 2, in the conventional dynamic burn-in test equipment, a large number of DUT boards 21, 22, 23, 24, . . . are stored in a thermostatic oven (or a thermostatic chamber) 1, and proper signals are supplied to the input pins of the DUT boards 21, 22, 23, 24, . . . by the test pattern generator 2 to monitor signals from output pins, thereby deciding the test results.
FIG. 3 is a block diagram for explaining a result decision circuit of the conventional general burn-in test equipment. A "high (H)" or "low (L)" value stored in a pattern memory 61 is transferred to an input terminal (input pin) of the DUT 21 through a driver 51, information appeared at an output terminal (output pin) of the DUT 21 is compared with an expected value by a comparator 53. An "H" or "L" expected value is stored in an expectation memory 64 in advance. The behavior or the result of the compared output terminal is stored in a result memory 65. In FIG. 3, although only one input pin and one output pin of one DUT 21 are shown, input/output terminals constituted by 100 to 500 pins are actually arranged on the DUT 21. A plurality of DUTs are stored in the thermostatic oven 1, and a plurality of result decisions are simultaneously required. All the input terminals can be parallel connected by a proper architecture in which series resistors are inserted into the terminals of the respective DUTs. However, values from the output terminals of the plurality of DUTs must be compared with the respective expected values by an independent comparator, and must be independently extracted.
FIG. 4 is a block diagram showing the conventional dynamic burn-in test equipment in which DUTs and pins are very much simplified. More specifically, FIG. 4 shows the connection topology between the three DUTs 21, 22, and 23 each having five input terminals IN1, IN2, . . . , IN5 and five output terminals OUT1, OUT2, . . . , OUT5 and the test pattern generator 2.
In a general burn-in test equipment, since a large number of DUTs 21, 22, and 23 are simultaneously tested, all the input terminals of the DUTs 21, 22, and 23 are electrically connected in parallel, and an equal signal is supplied from the test pattern generator 2 to the input terminals of the DUTs 21, 22, and 23. The output terminals of the DUTs 21, 22, and 23 need not be monitored for the purpose of the conventional burn-in testing. Then, the output terminals of the DUTs 21, 22, and 23 may be opened or subjected to a specific terminal connection topology. However, when a large number of defective products are produced, the conditions of the DUTs 21, 22, and 23 must be recognized during the testing by using the output terminals OUT1, OUT2, . . . , OUT5; OUT6, OUT7, . . . , OUT10; OUT11, OUT12, . . . , OUT15. More specifically, since signals of the output terminals must be extracted from the DUTs, the number of cables (N) which are running into or from the thermostatic oven satisfies the following equation: EQU N=P+n.multidot.Q+2 (2)
where P is the number of input pins of each DUT, Q is the number of output pins of each DUT, and n is the number of DUTs. The third term of the right side of Equation (2) is the number of power supply lines.
For example, in Equation (2) described above, the number of input pins P is set to be 100, the number of output pins Q is set to be 100, and the number of DUTs n in the board is set to be 30. In this case, a large value, i.e., N=3100 is obtained. In general, the number of output pins Q is large, the values P and Q may 200 or more. Therefore, in the conventional method, when the number of output pins becomes large, the value N becomes a value which cannot be realized. More specifically, only if the number of DUTs should be one to several, data represented by the bathtub curve shown in FIG. 1 could be obtained. Namely, the failure rate of a large number of DUTs cannot be actually measured because the equipment configuration becomes very complex and because a test time becomes extremely long. At present, since the number of output pins of an LSI chip tends to increase, the following problem is posed. That is, it is becoming more and more difficult or impossible that a failure rate of LSI chips is measured in a short test time and with a low cost.
As described above, in the conventional burn-in test equipment, a dynamic burn-in testing for monitoring all the outputs appeared at output terminals of DUTs to investigate all of the operations in an LSI chip cannot be realized.